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INTEGRATED CIRCUITS
DATA SHEET
74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger
Product specification Supersedes data of 1999 Aug 05 File under Integrated Circuits, IC06 1999 Sep 23
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
FEATURES * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V * Balanced propagation delays * Inputs accepts voltages higher than VCC * For AHC only: operates with CMOS input levels * For AHCT only: operates with TTL input levels * Output capability: standard * ICC category: flip-flops * Specified from -40 to +85 and +125 C. DESCRIPTION The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT74 dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. fmax CI CPD QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 3.0 ns.
74AHC74; 74AHCT74
TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay nCP to nQ, nQ nSD, nRD to nQ, nQ max. clock frequency input capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC AHCT CL = 15 pF; VCC = 5 V 3.7 3.7 130 VI = VCC or GND 4.0 12 3.3 3.7 100 4.0 16 ns ns MHz pF pF UNIT
Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. FUNCTION TABLES Table 1 See note 1 INPUT nSD L H L Table 2 nRD H L L See note 1 INPUT nSD H H nRD H H nCP nD L H OUTPUT nQn+1 L H nQn+1 H L nCP X X X nD X X X nQ H L H OUTPUT nQ L H H
Note to Tables 1 and 2 1. H = HIGH voltage level; L = LOW voltage level; X = don't care; = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition.
1999 Sep 23
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC74D 74AHC74PW 74AHCT74D 74AHCT74PW PINNING PIN 1 and 13 2 and 12 3 and 11 4 and 10 5 and 9 6 and 8 7 14 SYMBOL 1RD and 2RD 1D and 2D 1CP and 2CP 1SD and 2SD 1Q and 2Q 1Q and 2Q GND VCC data inputs
74AHC74; 74AHCT74
PACKAGE NORTH AMERICA 74AHC74D 74AHC74PW DH 74AHCT74D 74AHCT74PW DH TEMPERATURE RANGE -40 to +85 C PINS 14 14 14 14 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT108-1 SOT402-1 SOT108-1 SOT402-1
DESCRIPTION asynchronous reset-direct input (active LOW) clock input (LOW-to-HIGH, edge-triggered) asynchronous set-direct input (active LOW) true flip-flop outputs complement flip-flop outputs ground (0 V) DC supply voltage
handbook, halfpage
1RD 1D 1CP 1SD 1Q 1Q GND
1 2 3 4 5 6 7
MNA417
14 VCC 13 2RD 12 2D
handbook, halfpage
4 10 1SD 2SD 2 12 3 11 SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 1RD 2RD 1 13
MNA418
5 9
74
11 2CP 10 2SD 9 2Q
6 8
8 2Q
Fig.1 Pin configuration.
Fig.2 Logic diagram.
1999 Sep 23
3
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74AHC74; 74AHCT74
handbook, halfpage
4
1SD SD D CP FF Q RD 1Q 6 Q
2
handbook, halfpage
1D 1CP
1Q
5
4 3 2 1
S C1 1D R
5
3
6 1 1RD 2SD
10 11 12 13
S C1 1D R
MNA419
10 9 12 11
2D 2CP
SD D CP FF Q RD Q
2Q
8
9
2Q
8
13
2RD
MNA420
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
handbook, full pagewidth
Q C C
C C D C RD SD CP C C
C C Q C
MNA421
Fig.5 Logic diagram (one flip-flop).
1999 Sep 23
4
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage input voltage output voltage operating ambient temperature see DC and AC characteristics per device VCC = 5 V 0.5 V CONDITIONS MIN. 2.0 0 0 -40 -40
74AHC74; 74AHCT74
74AHCT UNIT TYP. MAX. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 V V V C
TYP. MAX. MIN. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 4.5 0 0 -40
+125 -40 100 20 - -
+125 C - 20 ns/V
tr,tf (t/f) input rise and fall rates
VCC = 3.3 V 0.3 V - -
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 C the value of PD derates linearly with 5.5 mW/K. PARAMETER DC supply voltage input voltage DC input diode current DC output diode current DC VCC or GND current storage temperature power dissipation per package for temperature range: -40 to +85 C; note 2 VI < -0.5 V; note 1 VO < -0.5 V or VO > VCC + 0.5 V; note 1 CONDITIONS MIN. MAX. UNIT -0.5 -0.5 - - - - -65 - +7.0 +7.0 -20 20 25 75 500 V V mA mA mA mA mW
DC output source or sink current -0.5 V < VO < VCC + 0.5 V
+150 C
1999 Sep 23
5
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
DC CHARACTERISTICS
74AHC74; 74AHCT74
74AHC family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH HIGH-level input voltage VCC (V) 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage; all outputs HIGH-level output voltage VI = VIH or VIL; IO = -50 A VI = VIH or VIL; IO = -4.0 mA VI = VIH or VIL; IO = -8.0 mA VOL LOW-level output voltage; all outputs LOW-level output voltage VI = VIH or VIL; IO = 50 A VI = VIH or VIL; IO = 4 mA VI = VIH or VIL; IO = 8 mA II IOZ ICC CI input leakage current 3-state output OFF current quiescent supply current input capacitance VI = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 MIN. 1.5 2.1 - - - 1.9 2.9 4.4 - - - - - 2.0 3.0 4.5 25 TYP. - - - 0.5 0.9 1.65 - - - - - 0.1 0.1 0.1 0.36 0.36 0.1 Tamb (C) -40 to +85 - - 0.5 0.9 1.65 - - - -40 to +125 UNIT - - 0.5 0.9 1.65 - - - V V V
MAX. MIN. MAX. MIN. MAX. 1.5 2.1 - - - 1.9 2.9 4.4 1.5 2.1 - - - 1.9 2.9 4.4 V
3.85 -
3.85 -
3.85 -
2.58 - 3.94 - - - - - - - - - - 0 0 0 - - - - - 3
2.48 - 3.8 - - - - - - - 0.1 0.1 0.1 0.44 0.44 1.0 2.5 20 10
2.40 - 3.70 - - - - - - - - - - 0.1 0.1 0.1 0.55 0.55 2.0
V
V
A
VI = VIH or VIL; 5.5 VO = VCC or GND VI = VCC or GND; IO = 0 5.5 -
0.25 - 2.0 10 - -
10.0 A 40 10 A pF
1999 Sep 23
6
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74AHC74; 74AHCT74
74AHCT family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage; all outputs HIGH-level output voltage VOL LOW-level output voltage; all outputs LOW-level output voltage II IOZ input leakage current 3-state output OFF current VI = VIH or VIL; IO = -50 A VI = VIH or VIL; IO = -8.0 mA VI = VIH or VIL; IO = 50 A VI = VIH or VIL; IO = 8 mA VI = VIH or VIL VCC (V) - - 4.5 25 - 0.8 - Tamb (C) -40 to +85 - 0.8 - -40 to +125 UNIT - 0.8 -
MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 - 4.4 2.0 - 4.4 V V V
4.5 to 5.5 2.0 4.5 to 5.5 - 4.5 4.4
4.5 4.5
3.94 - - 0
- 0.1
3.8 -
- 0.1
3.70 - - 0.1
V V
4.5 5.5
- - -
- - -
0.36 0.1
- -
0.44 1.0 2.5
- - -
0.55 2.0
V A
VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 VI = VCC or GND; 5.5 IO = 0 VI = VCC - 2.1 V other inputs at VCC or GND; IO = 0
0.25 -
10.0 A
ICC ICC
quiescent supply current additional quiescent supply current per input pin input capacitance
-
- -
2.0 1.35
- -
20 1.5
- -
40 1.5
A mA
4.5 to 5.5 -
CI
-
-
3
10
-
10
-
10
pF
1999 Sep 23
7
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
AC CHARACTERISTICS Type 74AHC74 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 15 pF - - 80 see Figs 6 and 8 50 pF - - 6.0 6.0 5.0 see Figs 6 and 8 6.0 0.5 50 5.2 5.4 125 7.4 7.7 - - - - - 75 11.9 12.3 - 15.4 15.8 - - - - - - CL MIN. 25 TYP.
74AHC74; 74AHCT74
Tamb (C) -40 to +85 -40 to +125 UNIT
MAX. MIN. MAX. MIN. MAX.
1.0 1.0 45 1.0 1.0 7.0 7.0 5.0 7.0 0.5 70
14.0 14.5 - 17.5 18.0 - - - - - -
1.0 1.0 45 1.0 1.0 7.0 7.0 5.0 7.0 0.5 70
15.0 15.5 - 19.5 20.0 - - - - - -
ns ns ns ns ns ns ns ns ns ns ns
propagation delay see Figs 7 and 8 nSD nRD to nQ, nQ fmax tPHL/tPLH maximum clock pulse frequency propagation delay nCP to nQ, nQ
propagation delay see Figs 7 and 8 nSD nRD to nQ, nQ tW clock pulse width HIGH or LOW set or reset pulse width LOW trem tsu th fmax removal time set or reset set-up time nD to nCP hold time nD to nCP maximum clock pulse frequency see Figs 6 and 8 see Figs 7 and 8
1999 Sep 23
8
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 15 pF - - 130 see Figs 6 and 8 see Figs 7 and 8 see Figs 6 and 8 see Figs 7 and 8 50 pF - - 5.0 5.0 3.0 see Figs 6 and 8 5.0 0.5 90 3.7 3.7 170 5.2 5.3 - - - - - 115 7.3 7.7 - 9.3 9.7 - - - - - - CL MIN. 25 TYP.
74AHC74; 74AHCT74
Tamb (C) -40 to +85 -40 to +125 UNIT
MAX. MIN. MAX. MIN. MAX.
1.0 1.0 110 1.0 1.0 5.0 5.0 3.0 5.0 0.5 75
8.5 9.0 - 10.5 11.0 - - - - - -
1.0 1.0 110 1.0 1.0 5.0 5.0 3.0 5.0 0.5 75
9.5 10.0 - 12.0 12.5 - - - - - -
ns ns ns ns ns ns ns ns ns ns ns
propagation delay see Figs 7 and 8 nSD nRD to nQ, nQ fmax tPHL/tPLH maximum clock pulse frequency propagation delay nCP to nQ, nQ propagation delay nSD to nQ, nQ tW clock pulse width HIGH or LOW set or reset pulse width LOW trem tsu th fmax Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. removal time set or reset set-up time nD to nCP hold time nD to nCP maximum clock pulse frequency
1999 Sep 23
9
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
Type 74AHCT74 GND = 0 V; tr = tf 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 15 pF - - 100 see Figs 6 and 8 50 pF - - 5.0 5.0 3.5 see Figs 6 and 8 5.0 0 80 3.3 3.7 160 4.8 5.3 - - - - - 140 7.8 10.4 - 8.8 11.4 - - - - - - CL MIN. 25 TYP.
74AHC74; 74AHCT74
Tamb (C) -40 to +85 -40 to +125 UNIT
MAX. MIN. MAX. MIN. MAX.
1.0 1.0 80 1.0 1.0 5.0 5.0 3.5 5.0 0 65
9.0 12.0 - 10.0 13.0 - - - - - -
1.0 1.0 80 1.0 1.0 5.0 5.0 3.5 5.0 0 65
10.0 13.0 - 11.0 14.5 - - - - - -
ns ns ns ns ns ns ns ns ns ns ns
propagation delay see Figs 7 and 8 nSD nRD to nQ, nQ fmax tPHL/tPLH maximum clock pulse frequency propagation delay nCP to nQ, nQ
propagation delay see Figs 7 and 8 nSD nRD to nQ, nQ tW tW(st)(rst) trem tsu th fmax Note 1. Typical values at VCC = 5.0 V. clock pulse width HIGH or LOW set or reset pulse width LOW removal time set or reset set-up time nD to nCP hold time nD to nCP maximum clock pulse frequency see Figs 6 and 8 see Figs 7 and 8
1999 Sep 23
10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
AC WAVEFORMS
74AHC74; 74AHCT74
handbook, full pagewidth
VI nD INPUT GND th t su 1/fmax VI nCP INPUT GND tW t PHL VOH nQ OUTPUT VOL VOH nQ OUTPUT VOL t PLH t PHL VM(1)
MNA422
VM(1)
th t su
VM(1)
t PLH
VM(1)
FAMILY AHC AHCT
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM(1) INPUT 50% VCC 1.5 V
VM(1) OUTPUT 50% VCC 50% VCC
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.6
The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
1999 Sep 23
11
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74AHC74; 74AHCT74
handbook, full pagewidth
VI nCP INPUT GND t rem VI nSD INPUT GND tW VI nRD INPUT GND t PLH VOH nQ OUTPUT VOL VOH nQ OUTPUT VOL t PHL t PLH VM(1)
MNA423
VM(1)
VM(1)
tW
VM(1)
t PHL
VM(1)
FAMILY AHC AHCT Fig.7
VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V
VM(1) INPUT 50% VCC 1.5 V
VM(1) OUTPUT 50% VCC 50% VCC
The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD to nCP removal time.
1999 Sep 23
12
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74AHC74; 74AHCT74
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL
MNA183
VO
1000
VCC open GND
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH open VCC GND
S1
Fig.8 Load circuitry for switching times.
1999 Sep 23
13
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm
74AHC74; 74AHCT74
SOT108-1
D
E
A X
c y HE vMA
Z 14 8
Q A2 A1 pin 1 index Lp 1 e bp 7 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
inches 0.069
0.010 0.057 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06S JEDEC MS-012AB EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-23 97-05-22
1999 Sep 23
14
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74AHC74; 74AHCT74
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04
1999 Sep 23
15
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering
74AHC74; 74AHCT74
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Sep 23
16
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74AHC74; 74AHCT74
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not REFLOW(1)
1999 Sep 23
17
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
NOTES
74AHC74; 74AHCT74
1999 Sep 23
18
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
NOTES
74AHC74; 74AHCT74
1999 Sep 23
19
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/02/pp20
Date of release: 1999
Sep 23
Document order number:
9397 750 06291

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